With the scaling of integrated circuits, more devices are put into a chip. This not only requires the shrinkage of the device size, but it also requires an improvement in the manufacturing techniques. One example involves memory chips. Due to the high capacity requirement of the memory chips, reducing layout area of the devices is especially important. Therefore, the devices in the memory chips are arranged close to each other to save space.
In the memory cell design, layout area, cell stability, and standby current are among the most important factors. Therefore, static random access memory (SRAM) cells have become the main stream in deep sub-micron technology. To achieve maximum density, the distance between devices in the SRAM cells, particularly the distance between N-well regions and P-well regions on which the devices of the SRAM cells are formed, needs to be as small as possible. This pushes the layout rules of lightly doped drain (LDD) regions of the MOS devices to their limit.
Increasingly more SRAM cells are formed of fin field-effect (FinFET) transistors, which have increased drive currents, and hence faster switching speed over that of planar transistors. Conventional formation of the LDD regions of the FinFETs in SRAM cells involves implants. The implantation, however, suffers from non-conformal doping, wherein the bottom portions of the fins have smaller LDD implantation depths than the top portions.